This invention relates generally to electronic interconnect structures, and in particular to interconnect stacks with fuse or anti-fuse links defined between profiled holes.
Electronic interconnect structures are known in the art. In their simplest form, these interconnect structures are embodied by printed circuit boards (PCBs) or printed wiring boards (PWBs). These types of boards use conductive traces or wire conductors to transmit electronic signals. One common application of PCBs and PWBs is in routing signals to and from electronic circuits and integrated circuits (ICs) in particular. In traditional PCBs the traces are provided in one or two planes; the top and bottom surfaces of the PCB. The number of traces which can be printed on a surface is limited by factors such as signal cross talk, current density and ohmic heating. Hence, traditional PCBs can only support a few hundred interconnections in PCBs of modest size and packing density.
More recently, multi-layered printed circuit boards (PCBs) have been employed to extend the number of interconnects by using several planes of traces. The planes are separated by dielectrics. Electrical connections between the planes are usually provided by vertical metal pillars or conductive vias.
Further information about multi-layered PCBs can be found in U.S. Pat. No. 4,498,122 entitled xe2x80x9cHigh-Speed, High Pin-Out LSI Chip Packagexe2x80x9d and other open literature.
Multichip modules (MCMs) are packages with high density substrates (finer than 100 xcexcm lines and spaces) and bare die (usually more than five). MCM is the current method used to interconnect multiple dice without adding substantial overhead in terms of volume and reliability.
The prior art also teaches more advanced interconnect structures in which interconnections can be programmed by establishing or breaking electrical connections. For example, U.S. Pat. No. 4,888,665 entitled xe2x80x9cCustomizable Circuitryxe2x80x9d, discloses interconnect circuits using orthogonally extending multi-wire layers adjacent ones of which can be fused and anti-fused as necessary to program interconnect nodes. Further teachings on multi-layered interconnect structures can be found in U.S. Pat. No. 4,899,439 entitled xe2x80x9cMethod of Fabricating a High Density Electrical Interconnectxe2x80x9d; U.S. Pat. No. 5,264,664 entitled xe2x80x9cProgrammable Chip to Circuit Board Connectorxe2x80x9d.
Multi-layered interconnect structures have also been used in flexible electrical wiring cables, as taught by U.S. Pat. No. 5,373,109 entitled xe2x80x9cElectrical Cable Having Flat, Flexible, Multiple Conductor Sectionsxe2x80x9d. It has also been recognized that it may be desirable, in certain applications to enhance component density by laterally stacking vertically oriented die or die-support substrates and providing for an edge connect. For information on such laterally stacked structures the reader is referred to U.S. Pat. Nos. 5,266,833; 4,983,533 and 4,764,846. Furthermore, it has been recognized that it may be desirable, in certain applications, to vertically stack horizontally-disposed dice in two or more layers. The reader is referred to U.S. Pat. Nos. 5,481,134; 5,481,133; 5,468,997; 5,455,445; 5,434,745 and 5,128,831 for a review of these teachings.
In U.S. Pat. Nos. 5,623,160 and 5,691,209 the present inventor discloses a signal-routing or interconnect substrate, structure and apparatus. The lattice is preferably formed in a plural-layer structure, whereby each required interconnect signal has one or more dedicated layers of a planar, thin-film conductor that is coextensive with the substrate. An array of vertical pillars or conductive vias is provided in the substrate, each pillar effectively providing an inner conductor either electrically connected with a conductive layer or electrically insulated therefrom by an insulative region. The pillars can be selectively connected or disconnected from the conductive layers by fusing and anti-fusing techniques.
Increasing density of ICs, whose linewidths (i.e., widths of conductive traces and pins) are constantly shrinking, have made current density a major concern in dense interconnect structures. Corresponding improvements to interconnect structures are documented in U.S. Pat. No. 5,969,321 to Smooha, who teaches how to avoid current crowding in a multi-layered interconnect structure by using two sets of separated vias. As well as in U.S. Pat. No. 5,973,396 to Farnworth who discloses an interconnect structure or die in which there can be vertical and horizontal fuse elements. Farnworth""s die permits one to decrease the die size or shrink the die stack.
Continuing increases in IC densities and reductions in die real estate demand further down-scaling and improvements to interconnect structures. Applications of interconnect stacks in fields other than pin-out of ICs place additional demands. For example, interconnect stacks have been proposed for use in memories. For further information the reader is referred to xe2x80x9cLaminated Memory: A New 3-Dimensional Packaging Technology for MCMsxe2x80x9d, proceedings of 1994 IEEE, Multichip Module Conference, pp. 58-63.
Several prior art approaches have focused on antifuse structures and materials. For example, U.S. Pat. No. 5,789,764 to McCollum teaches an antifuse material having a thickness designed to impart a desired target programming voltage to the antifuse. The antifuse can be used in via antifuses or stacked antifuses. Additional teaching on antifuse structures can be found in Chiang, xe2x80x9cAntifuse Structure Comparison for Field Programmable Gate Arraysxe2x80x9d, IEEE, IEDM, 1992, pp. 611-614; Cohen, xe2x80x9cA Flat-Aluminum Based Voltage-Programmable Link for Field-Programmable Devicesxe2x80x9d, IEEE Translations on Electronic Devices, vol. 41, No. 5, May 1994, pp. 721-724; Hu, xe2x80x9cInterconnect Devices for Field Programmable Gate Arrayxe2x80x9d, 1992, IEEE, IEDM, pp. 591-594; and Pauleau, xe2x80x9cInterconnect Materials for VLSI Circuitsxe2x80x9d, Solid State Technology, vol. 30, April 1987, pp. 155-162.
As a result of the advances made with wafer fabrication, today""s semiconductor chips are smaller, run at a higher frequency, generate more heat and require more interconnections due to increased complexity. The rapid increase in input/output (I/O) and space limitation requirements of new packaging place difficult demands on the interconnect density and electrical performance of package substrates. In chip-scale, area-array methods, a small form factor is needed, and there is no mechanism to accommodate the transition from the chip""s I/O density to the board""s density. Silicon shrinkage, advances in design tools, system architecture and package assembly have all driven higher densities. Bump pitch decreases for high-I/O-count packaging and shorter development cycles are pushing substrate suppliers to meet the new requirements.
Because packaging interconnect technology has not kept pace with the developments of the fabrication process and chip design, the current techniques for package interconnections are expensive and therefore prohibitive to mainstream applications. Presently, interconnection technology, or the lack thereof, is viewed as the major bottleneck in creating new electronic devices with higher performance, faster time-to-market, and lower costs.
Despite the various teachings related to MCM structures, further down-scaling remains a difficult task. It would be an advance in the art to provide an interconnect structure with fuse or antifuse type links which are more sensitive and permit further down-scaling of the interconnect structure. Specifically, it would be an advance in the art to develop more accurately and precisely controllable fuse and anti-fuse links in such interconnect structures.
Accordingly, it is a primary object of the present invention to provide an interconnect structure in the form of an interconnect stack having more precisely controlled fuse and/or anti-fuse links. In particular, it is an object of the invention to provide fuse and anti-fuse links which more accurately and precisely define the locations at which the fuse and anti-fuse processes take place, thereby allowing for further down-scaling of the interconnect stack.
These and other objects and advantages will be apparent upon reading the following description and accompanying drawings.
These objects and advantages are attained by an interconnect structure in the form of an interconnect stack consisting of a number of conductive planes and a number of insulating planes alternatingly disposed between the conductive planes. A number of conductive elements such as conductive vias extend generally normal to the conductive planes and insulating planes of the stack. The stack also has a number of profiled apertures which also extend generally normal to the conducting and insulating planes of the stack.
In one embodiment, the profiles apertures have appropriately selected geometrical shapes such that they define fuse links in one or more of the conductive planes. The fuse links have a steeply narrowed waist, such that a fusing current If passing through the fuse link produces a fused break substantially at the steeply narrowed waist. In other words, the fusing process occurring in the fuse links is localized to their steeply narrowed waist.
In one group of embodiments it is convenient for the profiled apertures to have corners. This can be accomplished by selecting the profiles of the apertures from among geometrical shapes including squares, rectangles and hexagons or any other geometrical shapes with corners. The profiled apertures are arranged such that the steeply narrowed waists of the fuse links are located substantially between two of the corners. In other words, the two corners of two adjacent apertures can be used to define the waist of each fuse link. Preferably, the steeply narrowed waist has a minimum width ranging from 100 xc3x85 to 1 mm.
In another group of embodiments, the profiled apertures have corners and edges and the steeply narrowed waist is located between at least one of the corners and at least one of the edges. Again, the profiles can be selected from among the same geometrical shapes as mentioned above. In this case, however, the adjacent apertures are placed in such that the corner of one approaches the edge of another at the steeply narrowed waist. The waist has a minimum width ranging from 100 xc3x85 to 1 mm.
In another embodiment, the profiled apertures have oval portions. In this embodiment the waist is preferably located between oval portions having a small radius of curvature.
In some cases it is convenient to associate a set of profiled apertures with each conductive via. For example, a set of four apertures can be associated with each conductive via. This association can be exclusive, in other words, the set of apertures associated with the one conductive via forms fuse links only around that one conductive via.
The interconnect structure of the invention can also be used with interconnect stacks with anti-fuse links. In this case, the apertures define anti-fuse links around the conductive vias and the steeply narrowed waist localizes the location of a fused joint. Specifically, passing an anti-fusing current Iaxe2x88x92f through the anti-fuse link produces a fused joint substantially at the steeply narrowed waist.
Once again, the profiles of the profiled apertures can be selected from among the same geometrical shapes as mentioned above the waists of the anti-fuse links can be located between corners or corners and edges of adjacent apertures. Furthermore, sets of apertures can be associated exclusively or non-exclusively with each conductive via to define, e.g., four anti-fuse links around each via.